Pranav Devalla, Hardware Design Engineer, Arista Networks
“As voltage drops and operating voltage ranges grow narrower, devices become more susceptible to noise.”
Power distribution networks (PDNs) are designed to accomplish two things. First, they must deliver the required DC power without dropping voltage, and second, they must have enough capacitance to supply current to whatever devices need the current. Every application has constraints that affect PDN design. For example, consumer electronics have more constraints in terms of using the lowest-power and least expensive components, and they must meet a different set of regulations compared with equipment used in data centers or industrial applications.
Simulation is an essential tool for balancing the many physical and design constraints that must be resolved in a successful PDN solution. However, even simulation tools can only get you so far because trends in device design requirements make achieving the essential PDN objectives more difficult.
For instance, over the past ten years, we have seen semiconductor process size shrink from 65 nanometers to 7 nanometers and now 5 nanometers. Chip manufacturers are working on designs that use 3- and 2-nanometer nodes. These small process sizes use fin field-effect transistors (FETs) and gate-all-around FETs that operate with higher switching speeds and lower voltages, and that is resulting in scaling down the voltage requirements of these devices. At the same time, with smaller process sizes, chip manufacturers are able to pack more and more onto a single chip, which increases these chips’ power requirements. Putting more of those high density components onto a
printed circuit board (PCB) makes power delivery even more challenging.
This is an excerpt from 7 Experts on New Approaches for Power Distribution
Network Design. The eBook was generously sponsored by KEMET Corporation and Mouser Electronics.
